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processing multiple pixels per clock in parallel enables fpga and asic hardware to process 4k, 8k, or high-frame-rate video streams. vision hdl toolbox™ natively supports multi-pixel-per-clock processing. its frame-to-pixels and pixels-to-frame gateway blocks offer easy settings to switch the design’s inputs and outputs from one pixel at a time to 4 or 8 in parallel, and its built-in blocks such as image filtering and edge detection natively support this mode.

to develop custom multi-pixel-per-clock algorithms, the line buffer block in vision hdl toolbox stores enough rows to form the neighborhood size you specify and outputs columns and control signals for 1, 4, or 8 pixels at a time.

the design shown is a custom implementation of the example from that uses built-in blocks. it shows how to use the line buffer to create four parallel neighborhood windows to be processed by a custom-designed image filter and edge detector. the parallel windows overlap significantly, so the design is architected to share these hardware resources. finally, it discusses hardware micro-architecture considerations such as register pipeline insertion and approaches to reduce multiplier usage while meeting latency requirements.